Method of operating a microprocessor

ABSTRACT

A method for operating a microprocessor (10) which can be switched by an activation signal (23) at an interrupt input (15) from an inactive operating state to an active operating state, with the activation signal (23) being supplied to the interrupt input (15) after a predeterminable time after each entrance into the inactive state.

BACKGROUND OF THE INVENTION

The invention is based on a method of operating a microprocessor thatcan be switched by a signal at one input from an inactive to an activeoperating state. WO 91/02303 discloses a wake-up circuit arrangement fora microprocessor which switches a microprocessor that has been switchedwith the aid of external signals into an inactive operating state backinto an active operating state. For each input signal, a separate inputcircuit is required. The input circuits decouple the individual inputsfrom one another and ensure defined loads at each one of the inputs.

It is the object of the invention to provide a particularly easilyimplemented method of operating a microprocessor which can be switchedfrom an inactive to an active operating state by a signal at one input.

SUMMARY AND ADVANTAGES OF THE INVENTION

The above object generally is achieved according to the presentinvention by a method of operating a microprocessor that can be switchedby a signal at one input from an inactive to an active operating state,wherein after entering the inactive state, the activation signal is fedto the input after a predeterminable time.

The method according to the invention has the advantage of aparticularly simple implementation and requires only a few components.The measure that, upon each transfer into the inactive state, theactivation signal is given to the input after a predetermined timeensures that the microprocessor reacts properly to input signals whichoccur only occasionally and are processed correspondingly rarely. Thetransition into the inactive state, which occurs, for example, under thecontrol of a program, reduces the residual current consumption of themicroprocessor which is of particular significance for battery suppliedsystems.

The predeterminable time during which the microprocessor is in theinactive state must be matched to the input signals to be expected.

Advantageous features and improvements of the method according to theinvention are disclosed and defined in the dependent claims.

The method according to the invention can be implemented particularlyeasily with a timer that receives a starting signal from themicroprocessor when the latter goes into the inactive state and which,at the end of the predetermined time, sends the activation signal to themicroprocessor.

According to another feature of the method according to the invention itis provided that a capacitor is charged with current by way of aterminal of the microprocessor during the active state and is dischargedduring the inactive state, with the activation signal being picked up atthe capacitor. In these methods it must merely be ensured that theterminals of the microprocessor through which the capacitor charging anddischarging current flows retain their function in the inactive state.An advantageous modification of this method provides that the capacitoris charged by way of a terminal of the microprocessor and is dischargedby way of a further terminal of the microprocessor. The particularadvantage of this modification is that the capacitor can be chargedquickly during the active state of the microprocessor and dischargedcomparatively slowly during the inactive state. This measure issignificant particularly if the active state is comparatively shortcompared to the inactive state. The predeterminable time for theinactive state may then be set to be relatively long compared to thetime for the active state.

This configuration is particularly easily implemented if ohmic resistorsare provided between each one of the microprocessor terminals and thecapacitor, with the value of the resistance influencing the chargingcurrent being lower than the value of the resistance influencing thedischarging current.

Further advantageous modifications and improvements of the methodaccording to the invention will become evident from the furtherdependent claims in conjunction with the following description.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1 and 2 are block circuit diagrams, each including amicroprocessor with which the method according to the invention isemployed.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIG. 1 depicts a microprocessor 10 which includes a program memory 11and an input/output unit 12. Microprocessor 10 is further provided withterminals 13, 14 for a current supply and a terminal 15 for an interruptinput.

The input/output unit 12 includes a terminal 16 which is connected withan external terminal 17. The external terminal 17 carries input signals18 as well as output signals 19 coming from microprocessor 10.

By way of a further terminal 20, input/output unit 12 feeds an outputsignal 21 to a timer 22 which in turn puts out an output signal 23 forinterrupt terminal 15. Timer 22 is connected at least to one of thecurrent supply terminals 13, 14.

The arrangement shown in FIG. 2 includes components which coincide withthose shown in FIG. 1. They therefore bear the same reference numeralsin FIG. 2 as in FIG. 1.

Input/output unit 12 includes two terminals 24, 25, with respectivelyconnected ohmic resistors 26, 27. An output signal 28 is put out by wayof terminal 24 and an input signal 29 is fed to terminal 25. Resistors26, 27 are connected to a capacitor 30 which is connected with a currentsupply terminal 14. Interrupt terminal 15 is connected to capacitor 30.

The method according to the invention will be described in furtherdetail with reference to the block circuit diagrams shown in FIGS. 1 and2.

The microprocessor 10 shown in FIG. 1 is a program controlled, signalprocessing arrangement which has integrated in it, for example, theprogram memory 11. The input/output unit 12 includes terminals 16, 20which can be switched as inputs or outputs depending on the program. Theterminal 16 connected with the external terminal 17 may, for example,pick up input signals and also put out output signals 19. In dependenceon the use of microprocessor 10, it may happen that microprocessor 10need not be constantly kept in its active operating state. Some types ofmicroprocessors 10, for example an MC 68 HC 04 P3 manufactured byMotorola Inc., are able to take on a residual energy saving, inactiveoperating state. The transition into the inactive state is controllable,for example, by a program contained in program memory 11. In some typesit is also possible to initiate the inactive operating state by an inputsignal over a separate input. The residual energy saving inactive stateof microprocessor 10 is of particular significance for battery operatedsystems. Such a use exists, for example, in motor vehicles which, atleast if the internal-combustion engine is shut off, are supplied withelectrical energy from a battery. In the off state of theinternal-combustion engine, a possibly provided alarm system or, forexample, a central locking system, both including a microprocessor 10,continue to require electrical energy. However, in these cases operationof microprocessor 10 is necessary only if, for example, an input signal18 is received by way of external terminal 17 at the terminal 16 ofinput/output unit 12, with such signal being put out, for example, by asignal generator of the central locking system. After a certain programthat is stored in program memory 11 has been run, with the active timelying, for example, in the microsecond range, microprocessor 10 can beswitched to the inactive state because the subsequent operating pauselies, for example, in the millisecond or second range or above. In theprior art, microprocessor 10 is therefore connected with partial systemsby way of connecting lines so as to switch microprocessor 10 to theactive operating state. If there are a plurality of input signals, it isnecessary, for example, to have an OR linkage and possibly a respectivedecoupling of individual lines. This comparatively great effort whichincurs costs, can be avoided with the method according to the invention.According to the invention it is provided that with each entrance in tothe inactive state on the part of microprocessor 10, the interruptterminal 15, after a predetermined time, receives an activation signal.In this connection, it is assumed that microprocessor 10 can be switchedinto the active operating state by way of interrupt input 15.

According to a first embodiment, a timer 22 is provided to put out theactivation signal as its output signal 23. After running a programstored in program memory 11, microprocessor 10 puts out an output signal21 by way of terminal 20 to timer 22. Then it changes to the inactivestate. The output signal 21 is a start signal for timer 22 which, at theend of the predetermined time, puts out the activation signal 23. Thepredeterminable time must be adapted to the minimum reaction time of thesystem including microprocessor 10. If an input signal 18 appears atexternal terminal 17 at irregular intervals for a certain minimumduration, the time of timer 22 must be set at less than the minimumsignal duration so that the signal is reliably detected.

At the end of the predeterminable time, microprocessor 10 switches intothe active operating state. If no signal is detected at externalterminal 17, to which a reaction should take place, microprocessor 10immediately emits another starting signal 21 for timer 22. A monostableflip-flop stage that is available as a finished component, for exampleunder the trade name CD 4047 is suitable as timer 22.

According to another feature of the method according to the invention,which will be described with reference to the block circuit diagramshown in FIG. 2, the timer 22 shown in FIG. 1 is initially replaced byresistor 26 and capacitor 30. During the active state of microprocessor10, the input/output unit 12 of microprocessor 10 puts out as its outputsignal 28, by way of terminal 24, a charging current across resistor 26to capacitor 30. Capacitor 30 is charged to a potential which is equal,for example, to the potential present at the current supply terminal 13of microprocessor 10. The charging duration is determined by the valueof resistor 26, the current and the capacitance of capacitor 30. Ifmicroprocessor 10 enters into the inactive state, output 24 is switchedas input, with capacitor 30 being discharged by way of the same resistor26. The discharging time is again determined by resistor 26, the currentand the capacitance of capacitor 30. With this configuration, a minimumratio of 1:1 for the active to the inactive state of microprocessor 10can be realized.

According to an advantageous modification of this method, a resistor 27is provided which is connected to terminal 25. During the active stateof microprocessor 10, capacitor 30 is charged by way of terminal 24which is connected as output. If the microprocessor changes to theinactive state, terminal 25 is switched as input and capacitor 30 isdischarged by way of resistor 27. The use of a discharging resistor 27that is separated from the charging resistor 26 has the particularadvantage that the charging and discharging times can be givenindependently of one another. It is thus possible to charge capacitor 30after a comparatively short duration of the active state and tocomparatively slowly discharge it during the inactive state. Thecharging and discharging currents are determined primarily by resistors26, 27 in conjunction with the operating voltage.

We claim:
 1. A method of operating a microprocessor comprising aninterrupt terminal, and an input/output unit having an input terminaland a separate output terminal, the microprocessor being programmable toswitch from an active operating state to an inactive operating state,said method comprising the steps of:(A) providing a timer having acharging resistor connected to the output terminal, a dischargingresistor connected to the input terminal, and a capacitor connected tothe charging resistor and the discharging resistor; (B) emitting acharging current through the output terminal and through the chargingresistor for charging the capacitor during the active operating state ofthe microprocessor; (C) discharging a discharge current from thecapacitor through the discharging resistor and through the inputterminal, beginning immediately upon the microprocessor entering theinactive operating state; (D) generating an activation signal independence on a discharged state of the capacitor; and (E) receiving theactivation signal at the interrupt terminal for switching themicroprocessor from the inactive operating state to the active operatingstate.
 2. The method as defined in claim 1, wherein the capacitor isdischarged during step (C) in a period of time that is greater than atime required for charging the capacitor during step (B).
 3. The methodas defined in claim 1, wherein the charging and discharging resistorsare respective ohmic resistors each located between the respectiveterminals of the microprocessor and the capacitor, with a value of acharging resistance of the charging resistor being less than a value ofa discharging resistance of the discharging resistor.